The present invention relates to a virtual storage system for handling a virtual address consisting of a segment number, a page number and displacement data (byte number) and, more particularly, to an address translation system for translating a virtual address into a real address.
A conventional virtual storage system of this type generally has a configuration as shown in FIG. 1. In the system shown in FIG. 1, in order to access a memory unit (to be referred to as an MU hereinafter) 3, processors (to be referred to as Ps hereinafter) 1 and input/output channels (to be referred to as CHs hereinafter) 2 transmit real addresses onto a system bus 4. For this purpose, each of the Ps 1 and CHs 2 has an address translation section (to be referred to as an ATS hereinafter) 5 which translates a virtual address into a real address. The real address on the system bus 4 is supplied to the MU 3 through a memory control unit (to be referred to as an MCU hereinafter) 6.
In the conventional virtual storage system of this type, since each processor and each channel has an ATS, the overall system becomes costly.
In order to solve this problem, a virtual storage system as shown in FIG. 2 has also been proposed. In the system shown in FIG. 2, in order to access an MU 13, Ps 11 and CHs 12 transmit virtual addresses onto a system bus 14. Therefore, the Ps 11 and CHs 12 do not each need to have an ATS. As is well known, a real address is required to access the MU 13. In the system shown in FIG. 2, an MCU 16 has an ATS 15 which translates a virtual address on the system bus 14 into a real address. A paging unit 18 is connected to the MCU 16.
In the conventional virtual storage system shown in FIG. 1, the virtual addresses are not assigned in one-to-one correspondence to all the information (all real addresses) stored in the MU 3. For example, the page table is stored only in the MU 3, that is, in a real storage, and a virtual address is not assigned to the page table. Furthermore, in the system shown in FIG. 1, the Ps 1 and CHs 2 handle both virtual and real addresses. For this reason, the Ps 1 can access (cache access) a cache memory (to be referred to as a CACHE hereinafter) 7 using a real address. Thus, even if a virtual address is not assigned to the page table, the Ps 1 can cache access a page table entry without any problem.
In contrast to this, in the virtual storage system shown in FIG. 2, the Ps 1 and CHs 2 handle only virtual addresses. For this reason, the P 11 must cache access the CACHE 17 using a virtual address. If a virtual address is not assigned to the page table in the same manner as in the system shown in FIG. 1, the Ps 11 cannot cache access the page table entry.
In order to allow a P 11 to cache access a table entry, a virtual address may be assigned to the page table. In order to assign a virtual address to the page table, the page table may be stored in a segment (first segment), i.e., a "V=R" segment, in which the virtual address coincides with the real address in a virtual address space (or a virtual storage) which is divided in units of segments.
However, the size (segment size) of the "V=R" segment is predetermined for each system. Therefore, if the number of pages constituting a segment is large, and the number of segments is also large, the page table cannot be stored within the "V=R" segment. Therefore, in the system shown in FIG. 2, it becomes difficult to support a large virtual address space.